RISC and ARM
- Physical constraints and market forces
- Parallelism
- Data have spatial and temporal characteristics. (Use adjacent data, migrate data to a cache.)
- Reduced Instruction Set Computer - makes common code fast. Don't worry about uncommon stuff.
- Reducing the semantic gap (1970s) in Intel caused problems with CISC.
- ARM processor is used in embedded/low-power environments, so it is RISC. Instruction set:
- Load/store (for RAM access) everything else is register to register. There are
32-bit registers. - R0..14 are general purpose registers. R15 is the program counter. CPSR: Current program status register.
- Little Endian: LSB = first addr. Big Endian:
78 56 34 12 3 2 1 0
OS Support and memory management
- Errors: divide by zero, illegal instructions, exceptions.
- Terminate flow and invoke the exception handler.
- Software interrupt handlers run at higher privileges.
- Hardware mechanism optimizes interrupts - adding extra registers is the only difficult part. The rest is similar to JMP.
ARM Tools
armcc -c hello.c armlink hello.o armcc -S hello.c
The -S produces assembler output.
Memories and parameter passing
- On RISC, choose registers for any instructions, except program counter PC which is r15. A calling convention for C is specified.
- ARM stacks grow downwards.
Intel instruction set
- General purpose register GPR0: EAX general purpose accumulator.
- x86 has very few registers.
- Segments pointers.
- Floating point registers -
80-bit in stack, also for MMX. - Complex instructions are difficult to decode.
- Addressing modes: Real and protected.
- Parameters on GPR0, 1, 2, 3, 6, 7.